Electrostatic chucks (ESCs) have been utilized in plasma-based or vacuum-based semiconductor processes such as etching, CVD, ion implantation, and the like. A typical ESC, for example, comprises a dielectric layer positioned over a conductive electrode, wherein the semiconductor wafer is placed on a surface of the ESC (e.g., the wafer is placed on a surface of the dielectric layer). During semiconductor processing (e.g., plasma processing), a clamping voltage is typically applied between the wafer and the electrode, wherein the wafer/workpiece is clamped against the clamp or chuck surface by electrostatic forces.
With the need for ever-increasing throughput and uniformity of semiconductor wafers, it is critical that the wafer be held firmly to the electrostatic clamp during processing. During a given process the wafer can experience up to 50 g forces and yet, it is critical to maintain wafer uniformity throughout the process and to un-clamp the wafer quickly once the processing is complete. Johnson-Rahbek (JR) clamps are routinely used in processing semiconductor wafers because of their ability to apply a large force to the wafer. In addition, it is critical that the wafer not slide on the clamp, as the clamping system would lose its frame of reference or index, and the backside of the wafer would suffer excessive particle contamination. JR clamps can apply a force to the wafer that is much larger than a Coulombic clamp, for example, however, the JR clamps take much longer to de-clamp, typically 10 seconds or greater. De-clamping or “un-sticking” the wafer from the chuck surface is a concern in many ESC applications. For example, after the electrostatic clamping voltage is turned off, the wafer cannot be removed by typical wafer lifting mechanisms (e.g., pins extending through the ESC which are operable to lift the wafer from the surface of the dielectric layer, edge grippers which are operable to lift the wafer, and the like). This wafer de-clamping problem can reduce the throughput of the wafer manufacturing process. It is believed that the current wafer de-clamping problem occurs when residual charges induced by the clamping voltage remain on the dielectric layer or on a surface of the wafer, therein leading to undesirable residual electric fields and clamping forces. According to a charge migration model, residual charges are caused by charge migration and accumulation during clamping, wherein the charges accumulate at the dielectric surface and/or wafer backside (e.g., when the wafer surface comprises an insulating layer). The clamp or wafer, by its very nature, is constructed of dielectric or semiconductor material that naturally inhibits the flow of charge.
As an extreme example, an RC time constant, can be used to characterize the charge/discharge times which correspond to the amount of time typically required to respectively clamp or de-clamp the wafer. This time constant is determined by the product of a volume resistance of the dielectric layer and a gap capacitance between the wafer and dielectric surfaces, i.e.,
                              R          ⁢                                          ⁢          C                =                                            R              die                        ⁢                          C              gap                                =                                    ρ              ⁡                              (                dielectric                )                                      ⁢                                                  ⁢                          ɛ              0                        ⁢                          ɛ              r                        ⁢                                          d                ⁡                                  (                  dielectric                  )                                            gap                                                          (        1        )            where Rdie is the resistance of the dielectric layer, Cgap is the capacitance of the gap between the wafer and the chuck surface, ρ (dielectric) is the volume resistivity of the dielectric layer, ε0 is the free space permittivity, εr is the dielectric constant of the gap, d(dielectric) is the thickness of the dielectric layer, and gap is the distance between the dielectric and wafer surfaces. For example, for a typical flat-plate ESC, if we assume that ρ(dielectric)=1015 Ω−cm, ε0=8.85×10−14 F/cm, εr=1, d(dielectric)=0.2 mm, and gap=3 μm, we find RC=5900 seconds. This is a fairly long charging/discharging time, meaning that if clamping is longer than 5900 seconds, the de-clamping time will also last approximately 5900 seconds.
FIG. 1 is a schematic illustration of a side view of a prior art Johnson-Rahbek (JR) clamp 22 that is currently used in industry. The JR clamp 22, as shown consists of a dielectric 10, an electrode 12, and a voltage source 14. By applying a positive voltage to the electrode 12, the voltage source 14 charges the electrode 12, to a positive state, as shown in FIG. 1. The dielectric 10 becomes charged as indicated by the positive charges 16 at the upper surface. In this type of JR clamp 22, the upper surface of the dielectric 10 is typically doped in order to make it more conductive, therefore a semiconductor. The smaller the gap, “g”, 18, the greater the electrostatic force between the wafer 20 and the electrostatic clamp 22. The electrostatic force is a function (1/g2) and therefore as the gap decreases, the force increases substantially.
One reason that the JR clamp 22 is difficult to separate from the wafer 20 is that the charge 16 at the top surface of the dielectric 10 has to drain out of the upper surface before it can release the wafer 20. In a Coulombic clamp (not shown), the wafer releases much faster because the charges are stored differently than they are in a JR clamp 22. However, a Coulombic clamp does not exert the strong forces like the JR clamp 22.
A variety of techniques have been previously disclosed for reducing wafer de-clamping problems encountered in the use of ESCs. For example, one conventional technique involves applying a reversal voltage before the wafer is removed from the ESC, therein eliminating a residual attractive force. This reversal voltage, however, is typically 1.5 to 2 times higher than the clamping voltage, and the de-clamping time is still typically quite large. Another conventional technique involves providing a low-frequency sinusoidal AC voltage in order to produce sine wave fields of controlled amplitude and phase in the clamp. Such low-frequency sinusoidal AC voltages, however, typically provide low clamping forces, as well as fairly long residual clamping times.
In addition, the cost of manufacturing an ESC tends to be very high. This is due in large part to the difficult manufacturing process involved in building an ESC. First, the chucking surface must be extremely flat, typically better than 15 μm, in order to reduce backside gas leakage, to increase thermal contact between the wafer and the ESC, and the like. Second, the dielectric material above the electrodes must be thin, about 150 μm to 1000 μm, in order to increase the clamping force exerted on the wafer, but also the material thickness must be very uniform, without pinholes, defects, etc., that can result in arcing between the wafer/workpiece and the electrode. Third, the dielectric material must be of extremely high purity, where the levels of contaminates do not exceed parts per million in composition, for example. Additionally, in the case of a JR type ESC, where the dielectric material is doped, for example, to make the ESC semiconductive, the dopant must be uniformly distributed throughout the material.
Therefore, a need exists in the art for a wafer/workpiece clamping/de-clamping system and method which is improved over the current art, as well as reducing the manufacturing cost and the overall cost of the electrostatic clamp.